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Freescale Semiconductor Technical Data
MPC9855 Rev 2, 1/2005
Preliminary Information Clock Generator for PowerQUICC and PowerPC Microprocessors
The MPC9855 is a PLL based clock generator specifically designed for Freescale Microprocessor and Microcontroller applications including the PowerPC and PowerQUICC. This device generates a microprocessor input clock. The microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. The device offers eight low skew clock outputs in two banks, each configurable to support different clock frequencies. The extended temperature range of the MPC9855 supports telecommunication and networking requirements. Features * 8 LVCMOS outputs for processor and other circuitry * Crystal oscillator or external reference input * 25 or 33 MHz Input reference frequency * Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33, or 16 MHz * Buffered reference clock output (2 copies) * Low cycle-to-cycle and period jitter * 100-lead PBGA package * 100-lead Pb-free Package Available * 3.3 V supply with 3.3 V or 2.5 V LVCMOS output supplies * Supports computing, networking, telecommunications applications * Ambient temperature range -40C to +85C * 100-lead PBGA package * 100-lead Pb-free Package Available
MPC9855
MICROPROCESSOR CLOCK GENERATOR
VF SUFFIX VM SUFFIX (Pb-FREE) 100 MAPBGA PACKAGE CASE 1462-01
Functional Description The MPC9855 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired. The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input frequency. The MPC9855 is packaged in a 100 lead MAPBGA package to optimize both performance and board density. ORDERING INFORMATION
Device MPC9855 Temp. Range -40C to +85C Case No. 1462-01 Package 100 lead MAPBGA
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
CLK PCLK PCLK CLK_SEL XTAL_IN XTAL_OUT XTAL_SEL
0 1 0 Ref 1 PLL OSC 2000 MHz
1 /N 0 QA1 QA2 QA3 /N QB0 QB1 QB2 QB3 QA0
PLL_BYPASS REF_33 MHz
CLK_A[0:5] CLK_B[0:5] REF_OUT0 MR REF_OUT1 REF_OUT1_E
Figure 1. MPC9855 Logic Diagram
MPC9855 2 Timing Solutions Freescale Semiconductor
Table 1. Pin Configurations
Pin CLK PCLK, PCLK QA0, QA1, QA2, QA3 QB0, QB1, QB2, QB3 REF_OUT0 REF_OUT1 XTAL_IN XTAL_OUT CLK_SEL XTAL_SEL REF_33 MHz REF_OUT1_E MR PLL_BYPASS CLK_A[0:5](1) CLK_B[0:5]1 VDD VDDA VDDOA VDDOB GND I/O Input Input Output Type Function Supply VDD VDD VDDOA Active/State -- -- --
LVCMOS PLL reference clock input (pull-down) LVPECL PLL reference clock input (PCLK -- pull-down, PCLK -- pull-up and pull-down) LVCMOS Clock Outputs
Output Input Output Input Input Input Input Input Input Input Input -- -- -- -- --
LVCMOS Reference Output (25 MHz or 33 MHz) LVCMOS Crystal Oscillator Input Pin LVCMOS Crystal Oscillator Output Pin LVCMOS Select between CLK and PCLK input (pull-down) LVCMOS Select between External Input and Crystal Oscillator Input (pull-down) LVCMOS Selects 33MHz input (pull-down) LVCMOS Enables REF_OUT! output (pull-down) LVCMOS Master Reset (pull-up) LVCMOS Select PLL or static test mode (pull-up) LVCMOS Configures Bank A clock output frequency (pull-up) LVCMOS Configures Bank B clock output frequency (pull-up) -- -- -- -- -- 3.3 V Supply Analog Supply Output Supply -- Bank A Output Supply -- Bank B Ground
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD -- -- -- -- --
-- -- -- High High High High Low High -- -- -- -- -- -- --
1. Power PC bit ordering (bit 0 = msb, bit 5 = lsb).
Table 2. Function Table
Control CLK_SEL XTAL_SEL PLL_BYPASS REF_OUT1_E REF_33 MHz MR Default 0 0 0 0 0 1 0 CLK CLKx Normal Disables REF_OUT1 Selects 25 MHz Reference Reset 1 PCLK XTAL Bypass Enables REF_OUT1 Selects 33 MHz Reference Normal
CLK_A and CLK_B control output frequencies. Refer to Table 3 for specific device configuration
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Table 3. Output Configurations (Banks A & B)
CLK_x[0:5](1) 111111 111100 101000 011110 010100 001111 001100 001010 001001 001000 000111 000110 000101 000100 CLK_x[0] (msb) 1 1 1 0 0 0 0 0 0 0 0 0 0 0 CLK_x[1] 1 1 0 1 1 0 0 0 0 0 0 0 0 0 CLK_x[2] 1 1 1 1 0 1 1 1 1 1 0 0 0 0 CLK_x[3] 1 1 0 1 1 1 1 0 0 0 1 1 1 1 CLK_x[4] 1 0 0 1 0 1 0 1 0 0 1 1 0 0 CLK_x[5] (lsb) 1 0 0 0 0 1 0 0 1 0 1 0 1 0 N 126 120 80 60 40 30 24 20 18 16 15 12 10 8(2) Frequency (MHz) 15.87 16.67 25.00 33.33 50.00 66.67 83.33 100.00 111.11 125.00 133.33 166.67 200.00 250
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) 2. Minimum value for N.
MPC9855 4 Timing Solutions Freescale Semiconductor
OPERATION INFORMATION
Output Frequency Configuration The MPC9855 was designed to provide the commonly used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values that will generate those common frequencies. The MPC9855 can generate numerous other frequencies that may be useful in specific applications. The output frequency (fout) may be calculated by the following equation. fout = 2000 / N where fout is in MHz and N = 2 * CLK_x[0:5] This calculation is valid for all values of N from 8 to 126. Note that N = 15 is a modified case of the configuration inputs CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to 00111 or 7. Crystal Input Operation The MPC9855 features a fully integrated Pierce oscillator to minimize system implementation costs. Other than the addition of a crystal no external components are required The crystal selection should be 25 MHz, parallel resonant type with a load specification of CL = 10 pF. The crystal should be located as close to the MPC92469 XTAL_IN and XTAL_OUT pins as possible to avoid any board level parasitic. Power-Up and MR Operation Figure 2 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. See Table 10 for actual parameter values. The MPC9855 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained.
VDD
MR treset_rel treset_pulse
Figure 2. MR Operation Power Supply Bypassing The MPC9855 is a mixed analog/digital product. The architecture of the XC9855 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VDD pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
VDD 22 F 15 VDDA 0.1 F 0.1 F VDD MPC9855
Figure 3. VCC Power Supply Bypass Power Consumption The total power consumption of the MPC9855 may be calculated by the following formula: P = VDD * (IDD + IDDA + IDDOC) + (CPD * frequency * * 4 * VDDOA**2) + (CPD * frequency * 4 * VDDOB**2) where frequency is the programmed output frequency for bank A and bank B.
MPC9855 Timing Solutions Freescale Semiconductor 5
Table 4. Absolute Maximum Ratings(1)
Symbol VDD VDDA VDDOA VDDOB VIN VOUT IIN IOUT TS Characteristics Supply Voltage (core) Supply Voltage (Analog Supply Voltage) Supply Voltage (LVCMOS output for Bank A) Supply Voltage (LVCMOS output for Bank B) DC Input Voltage DC Output Voltage(2) DC Input Current DC Output Current Storage Temperature -65 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max 3.8 VDD VDD VDD VDD+0.3 VDDx+0.3 20 50 125 V V mA mA C Unit V V V Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2. VDDx references power supply pin associated with specific output pin.
Table 5. General Specifications
Symbol VTT MM HBM CDM LU CIN CPD JC TA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Input Capacitance Power Dissipation Capacitance Thermal Resistance (junction-to-ambient) Ambient Temperature -40 200 2000 500 200 4 6 54.5 85 Min Typ VDD / 2 Max Unit V V V V mA pF pF Inputs Per Output Condition
C/W Air Flow = 0 C
Table 6. DC Characteristics (TA = -40C to 85C)
Symbol Characteristics Min Typ Max Unit Condition Supply Current for VDD = 3.3 V 5%, VDDOA = 3.3 V 5%, = VDDOB = 3.3 V 5% IDD + IDDA Maximum Quiescent Supply Current (Core) + IDDOC IDDA Maximum Quiescent Supply Current (Analog Supply) Supply Current for VDD = 3.3 V 5%, VDDOA = 2.5 V 5%, VDDOB = 2.5 V 5% IDD + IDDA Maximum Quiescent Supply Current (Core) + IDDOC IDDA Maximum Quiescent Supply Current (Analog Supply) 140 15 mA mA VDD + VDDA + VDDOC pins VDDIN pins 160 15 mA mA VDD + VDDA + VDDOC pins VDDIN pins
MPC9855 6 Timing Solutions Freescale Semiconductor
Table 7. LVPECL DC Characteristics (TA = -40C to 85C)(1)
Symbol Characteristics Min Typ Max Unit Condition Differential LVPECL clock inputs (CLK1, CLK1) for VDD = 3.3 V 0.5% VPP VCMR Differential Voltage(2) (peak-to-peak) Differential Input Crosspoint Voltage(3) (LVPECL) (LVPECL) 250 1.0 VDD - 0.6 mV V
1. AC characteristics are design targets and pending characterization. 2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew.
Table 8. LVCMOS I/O DC Characteristics (TA = -40C to 85C)
Symbol Characteristics Min Typ Max Unit Condition LVCMOS for VDD = 3.3 V 5% VIH VIL IIN Input High Voltage Input Low Voltage Input Current
(1)
2.0
VDD + 0.3 0.8 200
V V A
LVCMOS LVCMOS VIN = VDDL or GND
LVCMOS for VDD = 3.3 V 5%, VDDOA = 3.3 V 5%, VDDOB = 3.3 V 5% VOH VOL ZOUT Output High Voltage Output Low Voltage Output Impedance 14 - 17 2.4 0.4 V V IOH = -12 mA IOL = 12 mA
LVCMOS for VDD = 3.3 V 5%, VDDOA = 2.5 V 5%, VDDOB = 2.5 V 5% VOH VOL ZOUT Output High Voltage Output Low Voltage Output Impedance 18 - 22 1.9 0.4 V V IOH = -10 mA IOL = 10 mA
1. Inputs have pull-down resistors affecting the input current.
MPC9855 Timing Solutions Freescale Semiconductor 7
Table 9. AC Characteristics (VDD = 3.3 V 5%, VDDOA = 3.3 V 5%, VDDOB = 3.3 V 5%, TA = -40C to +85C)(1) (2)
Symbol fref Characteristics Input Reference Frequency (25 MHz input) Input Reference Frequency (33 MHz input) XTAL Input Input Reference Frequency in PLL Bypass Mode(3) fVCO fMCX VCO Frequency Range(4) Output Frequency Bank A output Bank B output Bank C output 15.87 15.87 50 2 100 80 47.5 45 50 50 500 52.5 55 1 10 10 10 2000 200 200 500 Min Typ 25 33 25 250 Max Unit MHz MHz MHz MHz MHz MHz MHz MHz ns ppm ns % 20% to 80% 3.3 V operation 2.5 V operation PLL locked Condition Input and Output Timing Specification
PLL bypass
frefPW frefCcc tr, tf DC
Reference Input Pulse Width Input Frequency Accuracy Output Rise/Fall Time Output Duty Cycle
PLL Specifications BW tLOCK treset_ref treset_pulse tsk(O) tsk(O) tJIT(CC) tJIT(PER) tJIT() 1. 2. 3. 4. PLL Closed Loop Bandwidth(5) Maximum PLL Lock Time MR Hold Time on Power Up MR Hold Time MHz ms ns ns
Skew and Jitter Specifications Output-to-Output Skew (within a bank) Output-to-Output Skew (across banks A and B) Cycle-to-cycle jitter Period Jitter I/O Phase Jitter RMS (1 ) 50 100 150 80 150 80 15 15 ps ps ps ps ps VDDOA = 3.3 V VDDOB = 3.3 V Bank A and B Back C Bank A and B Back C Bank A and B Back C
AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9855 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = (fVCO / M) N. 5. -3 dB point of PLL transfer characteristics.
Pulse Generator Z = 50
ZO = 50
ZO = 50
RT = 50 VTT
DUT MPC9855
RT = 50 VTT
Figure 4. MPC9855 AC Test Reference (LVCMOS Outputs)
MPC9855 8 Timing Solutions Freescale Semiconductor
Table 10. MPC9855 Pin Diagram (Top View)
1 A B C D E F G H J K VDDOA VDDOA RSVD VDDA XTAL_SEL PCLK CLK_SEL XTAL_IN VDDOB VDDOB 2 VDDOA VDDOA RSVD VDDA CLK PCLK REF_33MHz XTAL_OUT VDDOB VDDOB 3 CLKA[1] CLKA[0] VDD VDD VDD VDD VDD VDD CLKB[0] CLKB[1] 4 CLKA[3] CLKA[2] VDD GND GND GND GND VDD CLKB[2] CLKB[3] 5 CLKA[5] CLKA[4] VDD GND GND GND GND VDD CLKB[4] CLKB[5] 6 VDD QA0 VDD GND GND GND GND VDD QB0 VDD 7 QA1 VDDOA VDD GND GND GND GND VDD VDDOB QB1 8 QA2 QA3 VDD VDD VDD VDD VDD VDD QB3 QB2 9 VDDOA VDDOA VDD RSVD VDD RSVD PLL_BYPASS RSVD VDDOB VDDOB 10 VDDOA VDDOA REF_OUT[0] REF_OUT[1] GND RSVD MR REF_OUT1E VDDOB VDDOB
Table 11. MPC9855 Pin List
Signal VDDOA VDDOA CLKA[1] CLKA[3] CLKA[5] VDD QA1 QA2 VDDOA VDDOA VDDOA VDDOA CLKA[0] CLKA[2] CLKA[4] QA0 VDDOA QA3 VDDOA VDDOA 100 Pin MAPBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Signal RSVD RSVD VDD VDD VDD VDD VDD VDD VDD REF_OUT[0] VDDA VDDA VDD GND GND GND GND VDD RSVD REF_OUT[1] 100 Pin MAPBGA C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Signal XTAL_SEL CLK VDD GND GND GND GND VDD VDD GND PCLK PCLK VDD GND GND GND GND VDD RSVD RSVD 100 Pin MAPBGA E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Signal CLK_SEL REF_33MHz VDD GND GND GND GND VDD PLL_BYPASS MR XTAL_IN XTAL_OUT VDD VDD VDD VDD VDD VDD RSVD REF_OUT1E 100 Pin MAPBGA G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 Signal VDDOB VDDOB CLKB[0] CLKB[2] CLKB[4] QB0 VDDOB QB3 VDDOB VDDOB VDDOB VDDOB CLKB[1] CLKB[3] CLKB[5] VDD QB1 QB2 VDDOB VDDOB 100 Pin MAPBGA J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
MPC9855 Timing Solutions Freescale Semiconductor 9
PACKAGE DIMENSIONS
11
A1 INDEX AREA
B C K
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGING.
11
TOP VIEW
4X
0.2
SIDE VIEW
9X
1 0.5 5 0.35 A (1.18)
K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 100X 9X
1
1.7 MAX
0.43 0.29 0.5 0.55 0.45 0.25 0.10 3
M M
4
A
SEATING PLANE
100X
0.12 A
DETAIL K ABC A
ROTATED 90 CLOCKWISE
A1 INDEX AREA
BOTTOM VIEW
VA SUFFIX VM SUFFIX (Pb-FREE) 100 MAPBGA PACKAGE CASE 1462-01 ISSUE O
MPC9855 10 Timing Solutions Freescale Semiconductor
NOTES
MPC9855 Timing Solutions Freescale Semiconductor 11
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MPC9855 Rev. 2 1/2005

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